Looking for FPGA Programmer with RTL Design _ Santa Clara, CA _ 6 Month Contract

Send profile to: azhar@bravensinc.com

Job title: FPGA Programmer with RTL Design

Work Location: Santa Clara, CA

Duration: 6 Month contract

 

Job Description:

·             Component Design Engineer  position in the field of  Display pipeline related subsystem.

·             In this  position the candidate is responsible for  developing and verifying  new Display  new  protocol, Display Power saving techniques etc. on  FPGA.

·             Technical expertise in Verilog HDL  and strong FPGA prototyping Skills

·             Good Experience in RTL Design.

Thanks & Regards,

Azhar Ansari | Bravens Inc. I Talent Acquisition

Contact:714-786-6682         Fax: 281-404-9091

E Mail: azhar@bravensinc.com

Yahoo/Gtalk: azhar.bravensinc

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